In Re NETLIST, INC.

Case: 24-2304 Document: 97 Page: 1 Filed: 11/13/2026 NOTE: This disposition is nonprecedential. United States Court of Appeals for the Federal Circuit ______________________ IN RE NETLIST, INC., Appellant ______________________ 2024-2304 ______________________ Appeal from the United States Patent and Trademark Office, Patent Trial and Appeal Board in Nos. IPR2022- 00615, IPR2023-00203. ______________________ Decided: November 13, 2026 ______________________ JEFFREY A. LAMKEN, MoloLamken LLP, Washington, DC, argued for appellant. Also represented by JENNIFER ELIZABETH FISCHELL, KAYVON GHAYOUMI, RAYINER HASHEM, LIDIYA MISHCHENKO; ELIZABETH KATHLEEN CLARKE, Chicago, IL; CATHERINE MARTINEZ, New York, NY. ______________________ Before DYK, LINN, and CHEN, Circuit Judges. CHEN, Circuit Judge. Netlist, Inc. (Netlist) appeals the final written decision of the Patent Trial and Appeal Board (Board) determining that claim 16 of U.S. Patent No. 7,619,912 (’912 patent) was unpatentable under 35 U.S.C. § 103. Samsung Elecs. Case: 24-2304 Document: 97 Page: 2 Filed: 11/13/2026 2 IN RE NETLIST, INC. Co., Ltd. v. Netlist, Inc., No. IPR2022-00615, 2024 WL 1661650 (P.T.A.B. Apr. 17, 2024), No. IPR2022-00615, 2024 WL 1661650 (P.T.A.B. Apr. 17, 2024) (Decision). Be- cause the Board did not err in its claim construction, and substantial evidence supports the Board’s findings on pri- ority and obviousness, we affirm. BACKGROUND I The ’912 patent relates to “devices and methods for im- proving the performance, the memory capacity, or both, of memory modules” of a computer system. ’912 patent col. 1 ll. 21–24. The memory modules are comprised of memory devices, e.g., dynamic random-access memory (DRAM) de- vices, mounted on a circuit board, which includes a logic element. Id. col. 1 ll. 26–28; id. col. 2 ll. 47–50. These memory devices are arranged in rows, which are called “ranks.” Id. col. 2 ll. 16–18. The invention claimed in the ’912 patent aims to af- fordably increase the capacity of a memory module. It achieves this by arranging plural cheaper, lower-capacity memory devices to emulate fewer more expensive, higher- capacity devices. Extra memory devices can be added to the memory module either by increasing the number of memory devices per rank, by increasing the total number of ranks, or both. Emulating a different layout of memory devices creates challenges when it comes to coordination between a com- puter system and the improved memory module. During operation, the computer system sends control signals to the memory module that are intended to be transmitted to par- ticular (fictitious) memory devices in the relatively simple layout that the memory module is emulating. The memory module must intercept those control signals and create a new set of control signals that can be sent to the more com- plex layout of ranks and memory devices that the memory Case: 24-2304 Document: 97 Page: 3 Filed: 11/13/2026 IN RE NETLIST, INC. 3 module actually uses. The parties refer to this operation— intercepting the original control signals, creating a new set of control signals, and transmitting the new signals to the ranks of memory devices—as “rank multiplication.” Appel- lant Br. 10; Appellee Br. 10. The computer system also sends “command signals,” various commands that a memory device can execute such as “read” and “write.” ’912 patent col. 6 ll. 56–63; id. col. 8 ll. 44–47. Dependent claim 16, which depends from independent claim 15, is directed to the rank multiplication and recites: [16] A memory module connectable to a computer system, the memory module comprising: [a] a printed circuit board; [b] a plurality of double-data-rate (DDR) memory devices coupled to the printed cir- cuit board, the plurality of DDR memory devices having a first number of DDR memory devices arranged in a first number of ranks; [c] a circuit coupled to the printed circuit board, the circuit comprising a logic ele- ment and a register, [c.i] the logic element receiving a set of input signals from the com- puter system, the set of input sig- nals comprising at least one row/column address signal, bank address signals, and at least one chip-select signal, [c.ii] the set of input signals config- ured to control a second number of DDR memory devices arranged in a second number of ranks, the second number of DDR memory devices Case: 24-2304 Document: 97 Page: 4 Filed: 11/13/2026 4 IN RE NETLIST, INC. smaller than the first number of DDR memory devices and the sec- ond number of ranks less than the first number of ranks, [c.iii] the circuit generating a set of output signals in response to the set of input signals, the set of out- put signals configured to control the first number of DDR memory devices arranged in the first num- ber of ranks, [c.iv] wherein the circuit further re- sponds to a command signal and the set of input signals from the computer system by selecting one or two ranks of the first number of ranks and transmitting the com- mand signal to at least one DDR memory device of the selected one or two ranks of the first number of ranks; and [d] a phase-lock loop device coupled to the printed circuit board, the phase-lock loop device operatively coupled to the plurality of DDR memory devices, the logic element, and the register, [e] wherein the command signal is transmitted to only one DDR memory device at a time. ’912 patent col. 34 ll. 25–60 (emphases added). Case: 24-2304 Document: 97 Page: 5 Filed: 11/13/2026 IN RE NETLIST, INC. 5 II Samsung Electronics Co., Ltd. (Samsung)1 filed an in- ter partes review (IPR) of the ’912 patent. Relevant to this appeal, the petition argued that claim 16 was unpatentable under 35 U.S.C. § 103 in view of Patent Application US 2006/0277355 (Ellsberry). The Board instituted the IPR and later joined Micron Technology Inc., Micron Semicon- ductor Products, Inc., and Micron Technology Texas, LLC (collectively, Micron 2) as an additional petitioner in Sam- sung’s already-instituted IPR. The Board determined that claim 16 was unpatentable under § 103(a) in view of Ellsberry. The Board construed rank, concluding that a rank “can include only ‘one memory device.’” Decision, 2024 WL 1661650, at *10. The Board then concluded that the ’912 patent was not entitled to the earlier priority dates of U.S. Patent No. 7,286,436 (’436 pa- tent 3) or U.S. Provisional 60/588/244 (’244 provisional), both of which were filed before Ellsberry, due to lack of written-description support for claim 16. Id. at *14. Fi- nally, the Board concluded that Ellsberry disclosed ranks having a single memory device and therefore teaches or 1 On August 18, 2026, Samsung notified the court that it would not participate in this appeal. ECF No. 88. 2 After oral argument in this case, Micron filed its motion to withdraw in view of a settlement agreement it reached with Netlist. ECF No. 92. We granted Micron’s motion to withdraw. ECF No. 94. The United States Pa- tent and Trademark Office declined to intervene. ECF No. 96. Despite this withdrawal, a live controversy regarding the patentability of Netlist’s claims remains before us for resolution. See In re Rambus, Inc., 753 F.3d 1253, 1254 (Fed. Cir. 2014). 3 The ’912 patent is a continuation-in-part of U.S. Patent Application No. 11/075,395, filed on March 7, 2005, which issued as the ’436 patent. Case: 24-2304 Document: 97 Page: 6 Filed: 11/13/2026 6 IN RE NETLIST, INC. suggests limitation 16[e] (sending a command signal to only one DDR memory device at a time). Id. at *21–22. DISCUSSION “We review the Board’s ultimate determination of obvi- ousness de novo and its underlying findings of fact for sub- stantial evidence.” Virtek Vision Int’l ULC v. Assembly Guidance Sys., Inc., 97 F.4th 882, 886 (Fed. Cir. 2024). Claim construction is “a question of law, decided de novo on review, as are the intrinsic-evidence aspects of a claim- construction analysis. But we review any underlying fact findings about extrinsic evidence . . . for substantial-evi- dence support.” Intel Corp. v. Qualcomm Inc., 21 F.4th 801, 808 (Fed. Cir. 2021) (citation omitted). “Sufficiency of writ- ten description is a question of fact, reviewed for substan- tial evidence.” Parus Holdings, Inc. v. Google LLC, 70 F.4th 1365, 1373 (Fed. Cir. 2023). We first discuss the claim construction of rank. Then we turn to the Board’s finding that the ’436 patent and ’244 provisional lack written-description support for claim 16. Finally, we address whether substantial evidence supports the Board’s finding that Ellsberry discloses a command sig- nal “transmitted to only one DDR memory device at a time.” I As the Board observed, the parties’ claim construction dispute is limited entirely to the issue of “whether ‘rank’ can include just ‘one memory device.’” Decision, 2024 WL 1661650, at *6. The Board reasoned that claim 16 did not place explicit restrictions on the minimum number of memory devices in a rank. The Board also said that claim 55’s recitation that “each rank of the first number of ranks comprises a plurality of the DDR DRAM chip packages” would be superfluous if ranks could not consist of a single memory device. Id. at *6. Finally, the Board determined Case: 24-2304 Document: 97 Page: 7 Filed: 11/13/2026 IN RE NETLIST, INC. 7 that some embodiments in the specification disclosed ranks with only a single memory device. We adopt the Board’s construction that rank need not have a plurality of memory devices. We agree with the Board that the plain language of claim 16 does not impose any specific minimum number of memory devices in a rank. See ’912 patent at claim 16. Also, as the Board noted, the specification discloses ranks with single memory devices. Column 8 states that in some embodiments, a command signal is “passed through to both associated ranks,” and that in such embodiments, “the command signal . . . is sent to both memory devices.” ’912 patent col. 8 ll. 54–60. Be- cause the command signal is passed to “both” ranks and “both” memory devices, we agree with the Board’s conclu- sion that these embodiments had two memory devices, one in each of two ranks. See Decision, 2024 WL 1661650, at *8. We also agree that FIG. 6B illustrates “memory devices ‘a’ and ‘b’ of different ranks,” with no other memory devices shown on either rank. Decision, 2024 WL 1661650, at *8. Again, this shows that a rank does not need to have a plu- rality of memory devices. 4 4 The Board discussed a third embodiment of a rank lacking a plurality of memory devices in the ’912 patent’s specification: two examples of “Verilog code” that illustrate the operation of certain field-effect transistor (FET) switches in the claimed invention. Example 1 expressly in- cluded six FET switches, three of which correspond to memory devices in one rank and three of which correspond to memory devices in another rank. Example 2, however, contained just two FET switches, which Netlist’s expert conceded were in different ranks. The Board concluded that the inclusion of exactly two FET switches, one per rank, suggests that there was only one memory device in each of the two ranks. Case: 24-2304 Document: 97 Page: 8 Filed: 11/13/2026 8 IN RE NETLIST, INC. We reject Netlist’s various arguments. First, Netlist argues that by relying on claim 55, the Board misapplied the doctrine of claim differentiation. Appellant Br. 46–47. But claim 55 underscores that the patent drafter under- stood how to expressly impose a minimum number of memory devices in a rank if that requirement was desired. Second, Netlist challenges the specification’s examples of ranks that have only one memory device. Appellant Br. 48–50. In Netlist’s view, these examples show only zoomed-in examples of parts of the entire device. Id. We are not persuaded that column 8 and FIG. 6B depict only partial embodiments of its invention. Netlist contends that column 8 expounds upon the ’912 patent’s Table 1, and Ta- ble 1 uses the same labelling as the patent’s FIG. 1A, which depicts plural “memory devices” per rank. Appellant Reply Br. 17. But as the Board pointed out, column 8 describes “certain embodiments”—not necessarily the exemplary one in FIG. 1A. Decision, 2024 WL 1661650, at *8. And the labels “shared” by Table 1 and FIG. 1A are simply the names of the chip-select signals that are the inputs and outputs of the claimed logic element. The fact that two de- scriptions of circuits use the same nomenclature for some of their inputs and outputs does not necessarily show that they refer to the same circuit. Thus, the overlapping labels do not provide enough reason for us to determine that col- umn 8 describes only a partial embodiment of the inven- tion. We likewise reject Netlist’s argument that FIG. 6B “zoom[s]-in” on a pair of memory devices in two respective ranks that contain other memory devices not shown. The specification states that “FIG. 6B schematically illustrates Because we agree with the Board that column 8 and FIG. 6B both demonstrate that a rank can contain only one memory device, we need not consider the two Verilog ex- amples. Case: 24-2304 Document: 97 Page: 9 Filed: 11/13/2026 IN RE NETLIST, INC. 9 a circuit diagram of an exemplary memory module 10,” ’912 patent col. 24 ll. 28–31, without mentioning any zooming- in, simplification, or omissions. Third, Netlist contends that the Board deviated from the construction of rank that it adopted in previous reex- amination proceedings. 5 There, Netlist argues, the Exam- iner construed claim 16 to require “transmitting a command signal to only one DDR memory device at a time when there is a plurality of memory devices in a rank.” Ap- pellant Br. 33–34 (quoting J.A. 6375, 10561) (brackets and emphasis omitted). Based on this alleged construction, Netlist contends that it “disclaimed any construction that would cover sending commands to all devices in a rank, merely because a rank may have one device in it.” Id. But Netlist misunderstands the Examiner’s statement, which was not a claim construction. Instead, the Examiner 5 After the ’912 patent issued, Google and two other requesters sought inter partes reexamination. The Exam- iner found several claims unpatentable in view of U.S. Pa- tent Publication No. 2006/0117152 (Amidi). The ranks in Amidi’s memory module each contained a plurality of memory devices. See, e.g., Amidi at 2 ¶ 34 (stating, for ex- ample, that one rank contained memory devices “U1 through U9”). The ’912 patent’s claim 16 survived the reex- amination. The Examiner determined that the requesters had failed to demonstrate that Amidi would satisfy the lim- itation that a command signal be “transmitted to only one DDR memory device at a time” because “[r]equester has not provided a reasonable explanation as to why one skilled in the art would transmit a command signal to only one memory device at a time when there is a plurality of memory devices in a rank.” J.A. 6374–75. The Board up- held the reexamination. We affirmed. Google LLC v. Netlist, Inc., 810 F. App’x 902 (Fed. Cir. 2020) (per curiam). Case: 24-2304 Document: 97 Page: 10 Filed: 11/13/2026 10 IN RE NETLIST, INC. was explaining a shortcoming in the requester’s argument regarding a prior art reference Amidi: though the re- quester argued that a command signal can be transmitted to each memory device in one of Amidi’s ranks “in a sequen- tial fashion,” J.A. 6375, that argument was conclusory be- cause the requester did not explain why it would be preferable to transmit a command signal to each memory device sequentially in the situation where (1) there are a plurality of memory devices in a rank and (2) the command signal could be transmitted to all memory devices in the rank simultaneously. J.A. 6374–75; see also J.A. 10561. Thus, we do not view the Examiner’s statement as constru- ing rank at all, let alone construing it to require more than one memory device. Netlist counters that if the Examiner’s statement did not result in a disavowal of ranks with more than one de- vice, then the Examiner and Board could not have distin- guished Amidi in the reexamination because Amidi (like Ellsberry) discloses a memory module with ranks that have as few as one memory device per rank. Appellant Reply Br. 3–6. But regardless of whether Netlist is correct about the minimum number of memory devices per rank in Amidi, we will not reconstruct the Examiner’s reasoning from back to front so that it ends where Netlist wants it to. The prem- ise of the Examiner’s reasoning was that Amidi’s memory module contains multiple memory devices in a rank (and thus, the requester needed a nonconclusory explanation for why command signals would be transferred to the memory devices sequentially). Even if that premise misstated Amidi, we cannot convert the Examiner’s statement into a construction of the claim language in the ’912 patent. Fourth and finally, Netlist argues that a skilled artisan would have interpreted rank in view of a set of prevailing industry standards—the JEDEC standards—and that those standards require each rank to have multiple memory devices. Appellant Br. 38. We are not persuaded Case: 24-2304 Document: 97 Page: 11 Filed: 11/13/2026 IN RE NETLIST, INC. 11 that a skilled artisan would interpret rank in the ’912 pa- tent in view of the various JEDEC standards cited in the patent. Though Netlist argues that the claims “reference JEDEC’s ‘DDR’ standard,” Appellant Br. 39, the claims de- fine DDR simply as the abbreviation for double-data-rate. See ’912 patent col. 34 l. 28. Thus, the reference to DDR would not necessarily direct a skilled artisan to interpret other terms in the claims in view of JEDEC’s standards. Netlist also directs us to the ’912 patent’s specification, which lists several JEDEC standards among the references cited and incorporates the “JESD79D” JEDEC standard by reference, ’912 patent col. 12 ll. 39–43. Appellant Br. 39. Even if we were to agree that the JEDEC standards require more than one rank per device, we are not convinced that a skilled artisan would interpret rank in the claims in view of these standards. After all, that interpretation would be inconsistent with the specification’s examples of ranks con- taining a single memory device. Accordingly, we conclude that the Board correctly con- strued rank to allow as few as one memory device per rank. II We turn to the priority issue. Substantial evidence supports the Board’s findings that neither the ’436 patent nor the ’244 provisional contained written-description sup- port for claim 16. Decision, 2024 WL 1661650, at *14. A The Board found that the ’436 patent fails to disclose a circuit comprising a “register” as required by claim 16. De- cision, 2024 WL 1661650, at *13. Although the ’436 patent never mentions a register, Netlist argued that the ’436 pa- tent discloses a programmable logic device (PLD) that per- forms sequential logic, which a skilled artisan would have understood requires a register to store state values. But the Board rejected that argument, reasoning that even if a Case: 24-2304 Document: 97 Page: 12 Filed: 11/13/2026 12 IN RE NETLIST, INC. skilled artisan would infer the presence of a storage com- ponent, that storage role could be filled by other types of devices than a register, such as flip-flops and memory. 6 The Board thus disagreed with Netlist’s contention that the disclosed PLD necessarily requires a register. Substantial evidence supports the Board’s finding. Be- fore the Board, Netlist argued that a skilled artisan would understand that the ’436 patent discloses “a logic element to perform the logic functions (sequential and combinato- rial logic) and a register to store the ‘state register values.’” J.A. 1002 (emphasis added) (Netlist’s patent owner re- sponse). 7 The Board could reasonably find otherwise be- cause both experts agreed that what is inherent in the ’436 6 For the proposition that flip-flops and memory could serve as storage in a logic element performing se- quential logic, the Board cited a website that that the par- ties had not brought to the Board’s attention and that it apparently uncovered by performing independent re- search. Decision, 2024 WL 1661650, at *13 n.7. If we were required to consider the Board’s reliance on the website, it might give us pause. As Netlist argues, the Board’s review of the website in 2024 does not necessarily inform what a skilled artisan would have known at the time of the ’436 patent’s filing date almost two decades earlier, and Netlist had no opportunity to attempt to disqualify the website as a reference. But Micron did not defend the Board’s reliance on the website on appeal. See Oral Arg. at 21:10–21:25 (Mi- cron’s counsel stating that it has “agreed that that was im- proper, but it was not essential to the Board’s analysis”). 7 We do not consider Netlist’s argument on appeal that the ’436 patent’s disclosure provides written-descrip- tion support for a register or equivalent because Netlist’s argument before the Board contended only that the patent supported a register in particular. Case: 24-2304 Document: 97 Page: 13 Filed: 11/13/2026 IN RE NETLIST, INC. 13 patent’s disclosure is a storage element that would not nec- essarily need to be a register; it could also be a different element that serves the same purpose. J.A. 18694 (Sam- sung’s expert testifying that “sequential logic” requires “state storage in the form of a register or an equivalent”); J.A. 18345–46 ¶ 78 (Netlist’s expert declaring that sequen- tial logic would require “a storage or register component”); see Knowles Elecs. LLC v. Cirrus Logic, Inc., 883 F.3d 1358, 1365–66 (Fed. Cir. 2018) (rejecting the patent owner’s ar- gument that the specification necessarily provided written- description support where the specification disclosed a “ge- nus” but not the “claimed species,” even though that spe- cies was known in the art). 8 B The Board also found that the ’912 patent could not claim priority to the ’244 provisional. Decision, 2024 WL 1661650, at *14. Substantial evidence supports that find- ing as well. The Board’s analysis focused on whether the ’244 provisional disclosed “bank address signals” that are among the “set of input signals from the computer system” received by the “logic element,” as recited in claim 16. ’912 patent col. 34 ll. 34–37. The ’244 provisional does not men- tion bank address signals. And the Board reasonably found 8 Because we conclude that the ’436 patent lacked written-description support for a register, we do not reach Netlist’s argument that the Board separately erred by find- ing that a register that is part of the logic element would not satisfy the claim. See Appellant Br. 59–61. We also do not reach Netlist’s argument that it was not required to demonstrate the ’436 patent provided written-description support for each limitation of claim 16. See id. at 62–63. Case: 24-2304 Document: 97 Page: 14 Filed: 11/13/2026 14 IN RE NETLIST, INC. that a skilled artisan would need to make several consecu- tive inferences to conclude that the claimed bank address signals were inherently disclosed: [O]ne would have to (1) assume at least that the ’244 provisional pertains to DDR memory modules (when there is no mention of DDR and there were other types of DRAM devices on the market) be- cause Figure 1 suggests them by its use of chip se- lect signals and the term “rank,” and because they were the most common at the time; (2) understand that DDR DRAMs use bank address signals accord- ing to the JEDEC standards; (3) recognize that bank address signals are not mentioned in the ’244 provisional; (4) infer that bank address signals would be included as part of the control signals (even though the other address signals are explic- itly mentioned and set out separately); and (5) infer that the bank address signals are used for rank multiplication (when row/ and column/address could have been used for this purpose). Decision, 2024 WL 1661650, at *13. The Board determined that this chain of inferences was “too long and speculative” to conclude that the ’244 provisional provides written-description support for bank address signals going to a logic element. Id. We think this was reasonable because Netlist has not adequately ex- plained why a skilled artisan would make the final infer- ence in the chain. Netlist argues that claim 16 requires only the simpler inference that the bank address signals “be among the ‘set of input signals’ received by the ‘logic element,’ which ‘generates a set of output signals in re- sponse to the set of input signals.’” Appellant Br. 65 (brack- ets omitted). Even if that is so, Netlist makes no response to Samsung’s argument, noted by the Board, that a skilled artisan would not infer that bank address signals would be among the input signals that are received specifically by Case: 24-2304 Document: 97 Page: 15 Filed: 11/13/2026 IN RE NETLIST, INC. 15 the logic element. See Decision, 2024 WL 1661650, at *12 (noting the argument that control signals disclosed in the ’244 patent would not include bank address signals “be- cause those commands would go to the memory devices, and not to the logic performing rank multiplication”). Netlist argues only that a skilled artisan would have un- derstood that without bank address signals, the memory module would not be able to perform basic operations like “read” and “write,” Appellant Br. 64, without explaining why those operations require the bank address signals to be received at the logic element in particular. This failure is especially apparent because Samsung argued that the “read” and “write” operations would only require the bank address signals at the memory devices, not the logic ele- ment. J.A. 1202. We also reject Netlist’s argument that a skilled artisan would have read the ’244 provisional in view of the JEDEC standards and that “bank address signals undisputedly are ‘control signals’ in the JEDEC standard. Appellant Br. 63 (brackets omitted). As with the ’912 patent, the ’244 provi- sional does not limit itself to JEDEC compliance. III Finally, we address whether substantial evidence sup- ports the Board’s finding that Ellsberry discloses transmit- ting a command signal “to only one DDR memory device at a time” as required by claim 16. Decision, 2024 WL 1661650, at *22. We conclude that it does. Substantial evidence supports the Board’s finding that Ellsberry discloses ranks having a single memory device. The Board determined that Ellsberry FIG. 12 depicts a complete memory module with two ranks that each have one memory device. Decision, 2024 WL 1661650, at *21. Netlist argues that Ellsberry FIG. 12 shows only a partial, zoomed-in view of the complete ranks depicted in Ellsberry FIG. 2, which have multiple memory devices per rank. Ap- pellant Br. 51–52. But Ellsberry states that its FIGs. 10– Case: 24-2304 Document: 97 Page: 16 Filed: 11/13/2026 16 IN RE NETLIST, INC. 13 “illustrate different configurations of memory modules,” and does not at any point describe these figures as partial configurations of a larger embodiment. Ellsberry at 2 ¶ 21. Netlist contends that in a prior decision, the Board viewed FIG. 12 as depicting only part of an embodiment depicted in FIG. 2, and therefore, FIG. 12 does not show an embodiment with a single memory device in a rank. Ap- pellant Br. 54. But Netlist misstates the Board’s prior de- cision. There, the Board said only that Ellsberry “specifically relates” FIG. 12 and FIG. 2 when discussing whether a skilled artisan would have combined the differ- ent embodiments. J.A. 11986. Nothing in the Board’s prior decision suggested that FIG. 12 does not represent a sepa- rate embodiment. Finally, we reject Netlist’s assertion that having ranks with one memory device would defeat Ellsberry’s purpose of expanding the memory module’s capacity and render the module incompatible with JEDEC standards. As the ’912 patent teaches, the capacity of a memory module may be increased not only by “increasing the number of memory devices per rank” but also “by increasing the number of ranks.” ’912 patent col. 2 ll. 23–27. So Ellsberry’s goal of expanding memory capacity is not necessarily undermined by having only one memory device per rank. And even if having ranks with a single memory device would render Ellsberry incompatible with JEDEC standards, that can- not overcome Ellsberry’s express depiction of such a rank in FIG. 12. Thus, substantial evidence supports the Board’s find- ing that Ellsberry discloses a memory module that trans- mits a command signal to “only one DDR memory device at a time.” Decision, 2024 WL 1661650, at *21. Case: 24-2304 Document: 97 Page: 17 Filed: 11/13/2026 IN RE NETLIST, INC. 17 CONCLUSION We have considered Netlist’s remaining arguments and find them unpersuasive. For the foregoing reasons, we affirm. AFFIRMED