In Re NETLIST, INC.

Case: 25-1286 Document: 71 Page: 1 Filed: 11/13/2026 United States Court of Appeals for the Federal Circuit ______________________ IN RE NETLIST, INC. Appellant ______________________ 2025-1286, 2025-1296 ______________________ Appeals from the United States Patent and Trademark Office, Patent Trial and Appeal Board in Nos. IPR2023- 00454, IPR2023-00455, IPR2023-01141, IPR2023-01142. ______________________ Decided: November 13, 2026 ______________________ WILLIAM MILLIKEN, Sterne Kessler Goldstein & Fox PLLC, Washington, DC, argued for appellant. Also repre- sented by RICHARD M. BEMBEN, RICHARD CRUDO. ______________________ Before DYK, LINN, and CHEN, Circuit Judges. DYK, Circuit Judge. Appellant Netlist, Inc. appeals two decisions of the Pa- tent Trial and Appeal Board (“Board”) determining all claims of U.S. Patent Nos. 11,093,417 (“’417 patent”) and 9,858,215 (“’215 patent”) to be unpatentable as obvious. The Board found the patents to be obvious over U.S. Patent No. 7,363,422 to Perego et al. (“Perego”) in view of the DDR2 SDRAM Specification (“JESD79-2”) published by the Joint Electron Device Engineering Council (“JEDEC”). Case: 25-1286 Document: 71 Page: 2 Filed: 11/13/2026 2 IN RE NETLIST, INC. Netlist does not dispute that the combination of prior art Perego and JESD79-2 discloses the claim limitations of the patents. But Netlist argues that the Board erred in finding motivation to combine Perego and JESD79-2 be- cause the combination would be inoperable for the intended purpose of Perego, and because key benefits of Perego would be lost in the proposed combination. We conclude that the relevant question is whether the combination is operable for the purposes of the claimed invention; that the Board properly concluded that it was; and that the Board’s determination of motivation to combine was supported by substantial evidence. We affirm. BACKGROUND The patents concern improvements to computer memory architecture. Computer memory is typically pro- vided in memory modules, with each module comprising a set of memory chips and associated circuitry mounted on a printed circuit board. The architecture of computer memory ordinarily con- forms to industry specifications that define the physical and electrical properties of the modules and their compo- nents as well as how they interface with the computer’s memory controller. Among other differences, the various standards differ in how the individual memory chips are selected and addressed. According to one set of standards established by JEDEC, a global organization that develops and publishes standards for the microelectronics industry, memory chips were organized into ranks, which were se- lected or unselected for a given operation via a “chip-select” signal from the computer’s memory controller. J.A. 6998. Another set of standards was advanced by Rambus, Inc., a company that designed and licensed its own memory archi- tectures. Rambus architecture did not use chip-select sig- nals; instead, Rambus chips had unique device identifiers, such that a memory operation command could specify the unique chip for which it was intended. Case: 25-1286 Document: 71 Page: 3 Filed: 11/13/2026 IN RE NETLIST, INC. 3 Petitioners 1 challenged all claims of the ’417 and ’215 patents as unpatentable as obvious in inter partes review (“IPR”) proceedings before the Board. The ’417 and ’215 pa- tents are both titled “Memory Module with Data Buffer- ing.” ’417 patent Title; ’215 patent Title. The patents have substantially identical specifications disclosing “a memory module . . . operable in a computer system to communicate data with a memory controller of the computer system.” ’417 patent col. 3 ll. 18–20; ’215 patent col. 3 ll. 11–13. The parties agree that there are no material differences be- tween the claims of the ’215 patent and the ’417 patent for the purposes of this appeal. We therefore consider the ’417 patent and its corresponding IPR proceeding as being representative. Representative claim 1 of the ’417 patent recites (in- cluding reference numbers as used by the parties and the Board): [1.a.1] A memory module [1.a.2] operable in a com- puter system to communicate data with a memory controller of the computer system via a N-bit wide 1 Petitioners Samsung Electronics Co., Ltd., Micron Technology, Inc., Micron Semiconductor Products, Inc., and Micron Technology Texas, LLC were originally parties to these proceedings. Prior to oral argument in this appeal, Samsung Electronics settled with Netlist and filed a notice of nonparticipation. Dkt. No. 61; see Oral Argument at 0:00–0:25, In re Netlist, Inc., No. 24-2304 (Fed. Cir. Sept. 9, 2026). Subsequently, after oral argument, the Micron par- ties reached their own settlement with Netlist and with- drew from this appeal. Dkt. No. 65, 68. The United States Patent and Trademark Office declined to intervene. Dkt. No. 70. Despite this withdrawal, a live controversy regard- ing the patentability of Netlist’s claims remains before us for resolution. See In re Rambus, Inc., 753 F.3d 1253, 1254 (Fed. Cir. 2014). Case: 25-1286 Document: 71 Page: 4 Filed: 11/13/2026 4 IN RE NETLIST, INC. memory bus in response to read or write memory commands received from the memory controller, [1.a.3] the memory bus including address and con- trol signal lines and data signal lines, [1.a.4] the memory module comprising: [1.b] a printed circuit board having a plurality of edge connections configured to be electrically cou- pled to a corresponding plurality of contacts of a module slot of the computer system; [1.c.1] logic coupled to the printed circuit board and configurable to receive a set of input address and control signals associated with a read or write memory command via the address and control sig- nal lines and to output a set of registered address and control signals in response to the set of input address and control signals, [1.c.2] the set of input address and control signals including a plurality of input chip select signals and other input address and control signals, the plurality of input chip se- lect signals including one chip select signal having an active signal value and one or more other input chip select signals each having a non-active signal value, [1.c.3] the set of registered address and con- trol signals including a plurality of registered chip select signals corresponding to respective ones of the plurality of input chip select signals and other registered address and control signals correspond- ing to respective ones of the other input address and control signals, the plurality of registered chip select signals including one registered chip select signal having an active signal value and one or more other registered chip select signals each hav- ing a non-active signal value, [1.c.4] wherein the logic is further configurable to output data buffer control signals in response to the read or write memory command; Case: 25-1286 Document: 71 Page: 5 Filed: 11/13/2026 IN RE NETLIST, INC. 5 [1.d.1] memory devices mounted on the printed cir- cuit board and arranged in a plurality of N-bit wide ranks, [1.d.2] wherein the plurality of N-bit wide ranks correspond to respective ones of the plurality of registered chip select signals such that each of the plurality of registered chip select signals is re- ceived by memory devices [in] one respective N-bit wide rank of the plurality of N-bit-wide ranks, [1.d.3] wherein one of the plurality of N-bit wide ranks including memory devices receiving the reg- istered chip select signal having the active signal value and the other registered address and control signals is configured to receive or output a burst of N-bit wide data signals in response to the read or write command; and [1.e.1] circuitry coupled between the data signal lines in the N-bit wide memory bus and correspond- ing data pins of memory devices in each of the plu- rality of N-bit wide ranks, [1.e.2] the circuitry being configurable to transfer the burst of N-bit wide data signals between the N-bit wide memory bus and the memory devices in the one of the plurality of N-bit wide ranks in response to the data buffer control signals and [1.e.3] in accordance with an overall CAS latency of the memory module; [1.f] wherein data transfers through the circuitry are registered for an amount of time delay such that the overall CAS latency of the memory module is greater than an actual operational CAS latency of each of the memory devices. ’417 patent claim 1. Relevant to this appeal, in a memory module that uses “chip select signals,” claim 1 recites “circuitry” that serves as a buffer between the memory devices and the memory controller of a computer. Id. According to the patent, the Case: 25-1286 Document: 71 Page: 6 Filed: 11/13/2026 6 IN RE NETLIST, INC. buffer “advantageously isolates the ranks of memory de- vices of the memory module,” which “decreases the load on the computer system, thereby allowing the computer sys- tem . . . to run faster with improved signal integrity.” ’417 patent col. 10 ll. 5–43. However, the buffer may intro- duce a time delay between the memory devices and the computer’s memory controller. Id. col. 22 ll. 36–61. To ac- count for the delay, claim 1 also recites a “CAS latency” timing specification that reflects the amount of time delay imposed by the buffer. Id. claim 1 (limitations [1.e.3], [1.f]). Petitioners argued that the challenged claims were un- patentable as obvious over Perego in view of JESD79-2. Perego is a U.S. patent issued on April 22, 2008. Perego disclosed a “buffer device” that is “disposed on a memory module.” J.A. 7336 col. 3 ll. 15–16. 2 According to Perego, the buffer “provides for flexible system configurations” and “high bandwidth among a variety of possible module con- figurations in the system.” J.A. 7336 col. 3 ll. 23–28. JESD79-2 is an industry standard specification pub- lished by JEDEC in September 2003. JESD79-2 specifies various timing, signal, and configuration requirements (in- cluding chip select signals) for DDR2 SDRAM memory chips. In the Perego–JESD79-2 combination, petitioners re- lied on Perego’s buffer device as disclosing the ’417 patent’s “circuitry” limitations [1.e.1] and [1.e.2]. However, while Perego disclosed “address lines,” J.A. 7339 col. 9 ll. 58–60, it did not specifically disclose chip select signals. For this, petitioners relied on JESD79-2, which disclosed chip-select signals for selecting which rank is to be written to or read 2 Citations to “J.A.” refer to the Joint Appendix filed by the parties in this case. Dkt. No. 29. Case: 25-1286 Document: 71 Page: 7 Filed: 11/13/2026 IN RE NETLIST, INC. 7 from in a given operation. 3 On appeal, Netlist does not ar- gue that the combination of Perego and JESD79-2 would not satisfy the claim limitations. However, Netlist argued to the Board and argues to us that a POSA would have lacked motivation to combine. Ac- cording to Netlist, Perego disclosed only memory modules for the Rambus architecture, which was not compatible with the claimed chip-select signal characteristic of the competing JEDEC-compliant architectures. Netlist claimed that the combination would necessarily defeat the purpose of Perego to work with Rambus architecture, pointing out that the Board concluded that the proposed combination “would make Perego’s system non-functional for Rambus.” J.A. 29. Netlist also contended that conform- ing Perego to a JEDEC-compliant architecture would “crip- ple core functionalities described as benefits” in Perego, including maintaining the flexibility to support “new gen- erations of memory devices while retaining backward com- patibility with existing generations of memory devices.” J.A. 629 (quoting J.A. 7337 col. 6 ll. 39–43). In a final written decision of July 30, 2024, the Board determined that the combination disclosed each limitation of claim 1, a determination not challenged on appeal. The Board also determined that a POSA would be motivated to combine Perego and JESD79-2 based on indications in Per- ego that suggested amenability to JEDEC standards, Per- ego’s concern with flexibility to accommodate a variety of module configurations, and dominance of JEDEC stand- ards in the marketplace at the relevant time. The Board 3 Along with JESD79-2, petitioners also relied on JESD21-C, another JEDEC standard within the knowledge of a person of ordinary skill in the art (“POSA”) for the timing limitations of [1.e.3] and [1.f]. This reference is not material to this appeal and is not discussed further. Case: 25-1286 Document: 71 Page: 8 Filed: 11/13/2026 8 IN RE NETLIST, INC. held that the proposed combination rendered obvious all challenged claims. 4 Netlist timely appeals. We have jurisdiction under 28 U.S.C. § 1295(a)(4)(A). DISCUSSION In considering whether the Board erred in determining that the challenged patents were unpatentable as obvious, we review de novo the Board’s legal conclusion of obvious- ness, and we review the Board’s underlying factual deter- minations for substantial evidence. Shockwave Med., Inc. v. Cardiovascular Sys., Inc., 142 F.4th 1371, 1377 (Fed. Cir. 2025). Motivation to combine is a question of fact that we review for substantial evidence. Elekta Ltd. v. ZAP Surgical Sys., Inc., 81 F.4th 1368, 1374 (Fed. Cir. 2023). I Netlist’s primary argument is that Perego’s intended purpose was improvement of Rambus architecture, while petitioners’ proposed combination with JESD79-2 would have rendered Perego inoperable for Rambus. Appellant’s Br. 37–40. Netlist does not assert that Perego teaches away from the chip-select signals used in JESD79-2. In- stead, relying on cases such as In re Gordon, 733 F.2d 900, 902 (Fed. Cir. 1984), Netlist argues that a POSA would not have been motivated to make a combination that was non- functional for Rambus. So too Netlist argues that the com- bination would not have served a related purpose of Perego to have backward compatibility, the ability to implement a memory module using earlier generations of memory de- vices. Netlist misconceives the law of obviousness. As the Su- preme Court noted in KSR International Co. v. Teleflex 4 The Board did not reach petitioners’ other asserted obviousness grounds. Case: 25-1286 Document: 71 Page: 9 Filed: 11/13/2026 IN RE NETLIST, INC. 9 Inc., “familiar items may have obvious uses beyond their primary purposes, and in many cases a person of ordinary skill will be able to fit the teachings of multiple patents to- gether like pieces of a puzzle.” 550 U.S. 398, 420 (2007). We have made clear that “[w]hen an obviousness challenge asserts a combination of identified prior art, the motiva- tion-to-combine portion of the inquiry is whether a skilled artisan would have been motivated to combine the teach- ings of the prior art references to achieve the claimed in- vention.” Axonics, Inc. v. Medtronic, Inc., 73 F.4th 950, 957 (Fed. Cir. 2023) (internal citations and quotation marks omitted) (emphasis in original). “The inquiry is not whether a relevant artisan would combine a first refer- ence’s feature with a second reference’s feature to meet re- quirements of the first reference that are not requirements of the claims at issue.” Id. Thus, in Axonics, the primary reference disclosed a neural electrode for stimulating a particular nerve. See id. at 954, 957–58. This electrode was used in a combination for stimulating a different nerve targeted in the challenged patent. Id. We held that it was irrelevant that the modi- fied nerve electrode could not function for the nerve origi- nally targeted in the primary reference. See id. at 957–58. We have often confirmed that in a motivation-to-combine analysis, “the intended purpose of [the prior art] does not control.” E.g., Intel Corp. v. Qualcomm Inc., 21 F.4th 784, 800 (Fed. Cir. 2021). Thus, in this case, what matters is whether a skilled artisan would have had an adequate rea- son to modify Perego to be amenable to JEDEC stand- ards. See, e.g., Axonics, 73 F.4th at 957. Here, compatibility with Rambus was not the purpose of the claimed invention, and backward compatibility was not an objective of the claimed invention. Rather, the claimed invention is directed to the ability to function in a JEDEC-compliant architecture. The fact that the combi- nation was not compatible with Rambus and would not Case: 25-1286 Document: 71 Page: 10 Filed: 11/13/2026 10 IN RE NETLIST, INC. serve the backward-compatibility objectives of Perego is ir- relevant. To be sure, there are limited circumstances where the purpose of the prior art device is pertinent; for example, where the alleged motivation to combine comes from the functionality of the invention disclosed in the prior art pub- lication, rather than from another source. That was the case in Gordon. There, we considered a challenge to a pa- tent claiming a blood-filter assembly with the blood inlet and outlet both located at the “bottom end” of the assembly. Gordon, 733 F.2d at 901. The asserted prior art was a gas- oline filter with the inlet and outlet located at the top of the filter. Id. We reasoned that the position of the ports af- fected the operation of the prior-art filter, which relied on gravity to cause the lighter gasoline to float to the top and allow the denser contaminants to sink. See id. at 902. We concluded that inverting the prior art device would make it inoperable for its intended purpose such that the prior art effectively taught away from the inversion. 5 Id. When a prior-art reference itself supplies the asserted motivation to combine, it is logical to assume that the ref- erence would not suggest to a POSA to modify its disclosed embodiments in a way that contravenes its own contem- plated purposes. See Gordon, 733 F.2d at 902. But that is not the situation here. Petitioners did not rely on Perego’s Rambus capabilities to establish motivation to combine. 5 In Adidas AG v. Nike, Inc., 963 F.3d 1355 (Fed. Cir. 2020), we upheld the Board’s determination that factors outside the references themselves did not support motiva- tion to combine, and “fundamental differences in the seam- ing techniques” of the asserted textile-related references precluded a justification for motivation to combine from be- ing found within the references themselves. Id. at 1359– 60. Case: 25-1286 Document: 71 Page: 11 Filed: 11/13/2026 IN RE NETLIST, INC. 11 Nor did they rely on Perego’s backward-looking compatibil- ity with Rambus to support a motivation to combine. The purpose of the prior art may also be relevant where the prior art has a “purpose [that is] shared with the chal- lenged claims.” Medtronic, Inc. v. Teleflex Innovations S.à.r.l., 69 F.4th 1341, 1350 (Fed. Cir. 2023). This case is not a situation where the defeated purpose was a shared purpose, as in cases such as Polaris Industries, Inc. v. Arc- tic Cat, Inc., 882 F.3d 1056 (Fed. Cir. 2018), and Medtronic. In Polaris, we considered an IPR challenge to patent claims reciting an all-terrain vehicle with a fuel tank placed below a seat. 882 F.3d at 1060, 1067. The specification of the challenged patent touted the benefits of a low center of gravity. Id. at 1059–60. The petitioner in that case pro- posed the combination of a first reference disclosing an all- terrain vehicle having a lower center of gravity than tradi- tional vehicles with a second reference disclosing a vehicle having a below-seat fuel tank. Id. at 1061–62. We rejected the Board’s conclusion on motivation to combine because it was undisputed that the combination relocating the fuel tank would “rais[e] the center of gravity and render[] the vehicle less stable.” Id. at 1069. The low center of gravity was an important shared feature of the claimed invention and the prior-art reference. See id. at 1059–61. The fact that the combination would defeat this shared purpose counseled against finding a motivation to combine. In Medtronic, we similarly rejected a proposed combi- nation that undermined a prior-art reference’s “entire pur- pose” that was “shared with the challenged claims” and we also recognized that Polaris was predicated on a modifica- tion that would undermine a goal shared with the chal- lenged claims. 69 F.4th at 1349–50. So too in Chemours Co. FC, LLC v. Daikin Industries, Ltd., this court rejected a petitioner’s proposed combination discarding a “key fea- ture” that eroded the shared purpose of achieving high- speed extrusion of polymer coatings. 4 F.4th 1370, 1375 (Fed Cir. 2021). Here, neither Rambus compatibility nor Case: 25-1286 Document: 71 Page: 12 Filed: 11/13/2026 12 IN RE NETLIST, INC. backward compatibility with Rambus architecture was a shared purpose of the invention. Netlist argues only that the proposed combination is inoperable for Perego’s intended purposes, not the pur- poses of the claimed invention as in Polaris, Medtronic, and Chemours. And Netlist does not argue that Perego sup- plied the motivation to combine. Thus, the Board did not err by finding a motivation to combine in which the combi- nation was “non-functional for Rambus, [but] not for JEDEC” or where the combination lost backward compati- bility with Rambus memory devices. 6 J.A. 27–29. 6 Netlist argues that the Board ignored its back- ward-compatibility argument in violation of the Adminis- trative Procedure Act (“APA”). According to Netlist, the Board did not address the argument that the Perego– JESD79-2 modification “would defeat [Perego’s] very sup- port for ‘new generations of memory devices while retain- ing backward compatibility with existing generations of memory devices.’” J.A. 629 (quoting J.A. 7337 col. 6 ll. 39– 44). We disagree. The Board addressed this point, includ- ing by quoting and discussing the portion of Perego identi- fied by Netlist: Perego further discloses that its buffered module provides flexibility because “new generations of controllers may be phased in which exploit features of new generations of memory devices while retain- ing backward compatibility with existing genera- tions of memory devices.” [J.A. 7337 col. 6 ll. 34– 43.] In this context, it makes sense that Perego would leave the option open to use a bus on the in- terface between the module and the controller and not be limited to a point-to-point system, which would limit the ability to interface with a system that uses a bus, such as a JEDEC system. Case: 25-1286 Document: 71 Page: 13 Filed: 11/13/2026 IN RE NETLIST, INC. 13 II Netlist further argues that Perego does not suggest im- plementing a JEDEC-compliant memory module and that neither the Board nor petitioners “provided any other mo- tivation to combine Perego with JEDEC module stand- ards.” Appellant’s Br. 57. To the contrary, the Board found several reasons supporting motivation to combine, and its findings are supported by substantial evidence. The Board found that Perego itself suggested alterna- tive embodiments compatible with JEDEC but not with Rambus. The Board recognized that Perego disclosed “bussed topologies” as an alternative to Rambus’s “point- to-point link.” J.A. 23 (citing J.A. 7338 col. 8 ll. 42–47, 51– 65). The Board determined that Perego disclosed memory modules with a 64-bit data width and that there was evi- dence that a 64-bit width was standard in JEDEC modules and wider than the 36-bit maximum used in the Rambus architecture. J.A. 23–24 (citing J.A. 7341 col. 14 ll. 16–23). The Board also recognized that Perego disclosed “row ad- dress strobe” and “column address strobe” lines that are used in JEDEC architectures, but not Rambus. J.A. 25– 27; J.A. 7339 col. 9 ll. 58–60. Regardless of whether such signals uniquely signify a JEDEC-compliant architecture, their disclosure in Perego is inconsistent with Netlist’s con- tention that Perego was Rambus-only. There was substan- tial evidence to support the Board’s conclusion that Perego disclosed alternative embodiments amenable to JEDEC ar- chitectures. The Board further observed that Perego disclosed that “[t]here is a need for memory system architectures or inter- connect topologies that provide flexible and cost effective upgrade capabilities,” and that “bussed approaches,” such J.A. 27. Case: 25-1286 Document: 71 Page: 14 Filed: 11/13/2026 14 IN RE NETLIST, INC. as in a JEDEC system, “permit[] module interfacing for up- gradeability.” J.A. 28 (quoting J.A. 7335 col. 2 ll. 22–29). The Board also concluded from Perego’s disclosure that its buffer may “‘provide upgrade flexibility . . . among a va- riety of possible module configurations’” that “Perego’s dis- closure is concerned with more than just one type of memory module.” J.A. 27 (emphasis in original) (quoting J.A. 7336 col. 3 ll. 25–28). The Board determined—supported by Netlist’s own ex- pert testimony—that “JEDEC-compliant modules were dominant in the market at the relevant time,” providing a motivation to produce a module that was JEDEC compli- ant. J.A. 28 (citing J.A. 14015 ¶ 72). Netlist does not con- test that JEDEC had become dominant at the time of invention of the ’417 patent, or that the combination was JEDEC capable. This was substantial evidence supporting the Board’s determination that a POSA would have been motivated to combine Perego with JESD79-2. CONCLUSION The Board determined that the combination of Perego with JESD79-2 was operable for the purpose of the chal- lenged patents, and that a POSA would have been moti- vated to combine Perego with JESD79-2. We conclude that these determinations were supported by substantial evi- dence. Accordingly, we affirm. AFFIRMED